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a ad7660 16-bit, 100 ksps pulsar unipolar cmos adc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s. a. tel:7 8 1 / 3 2 9 -470 0 www.a nal og. c om fax:7 8 1 / 3 2 6 -8703 ?2001-2016 analog devices, inc. all rights re s e rve d. rev. e functional block diagram switched cap dac 16 control logic and calibration circuitry clock ad7660 d[15:0] busy rd cs ser/par ob/2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst features throughput: 100 ksps inl: 3 lsb max ( 0.0046% of full-scale) 16-bit resolution with no missing codes s/(n+d): 87 db min @ 10 khz, 90 db typ @ 45 khz thd: ?6 db max @ 10 khz analog input voltage range: 0 v to 2.5 v both ac and dc specifications no pipeline delay parallel and serial 5 v/3 v interface spi / qspi/mi crowire/ dsp compatible single 5 v supply operation 21 mw typical power dissipation, 21 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flatpack (lqfp) 48-lead chip scale package (lfcsp) pin-to-pin compatible with the ad7664 applications data acquisition battery-powered systems pcmcia instrumentation automatic test equipment scanners medical instruments process control general description the ad7660 is a 16-bit, 100 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. the part contains an internal conversion clock, error cor- rection circuits, and both serial and parallel system interface ports. the ad7660 is hardware factory-calibrated and is comprehen- sively tested to ensure ac parameters such as signal-to-noise ratio (snr) and total harmonic distortion ( thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it is fabricated using analog devices?high performance, 0.6 micron cmos process with correspondingly low cost and is available in a 48-lead lqfp and a tiny 48-lead lfcsp with operation specified from ?0 c to +85 c. product highlights 1. fast throughput the ad7660 is a 100 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 2. superior inl the ad7660 has a maximum integral nonlinearity of 3 lsbs with no missing 16-bit code. 3. single-supply operation the ad7660 operates from a single 5 v supply and only di ssipates 21 mw typical. its power dissipation decreases with the throughput to, for instance, only 21 m w at a 100 sps t hroughput. it consumes 7 m w maximum when in power-down. 4. serial or parallel interface versatile parallel or 2-wire serial interface arrangement com- patible with both 3 v or 5 v logic. table i. pulsar selection type/ksps 100?50 500?70 800?000 pseudo ad7651 ad7650/ad7652 ad7653 differential ad7660/ad7661 ad7664/ad7666 ad7667 true bipolar ad7663 ad7665 ad7671 true ad7675 ad7676 ad7677 differential 18-bit ad7678 ad7679 ad7674 simultaneous/ ad7654 multichannel ad7655
ad7660* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7660 evaluation kit documentation application notes ? an-931: understanding pulsar adc support circuitry ? an-932: power supply sequencing data sheet ? ad7660: 16-bit, 100 ksps pulsar ? unipolar cmos adc data sheet product highlight ? 8- to 18-bit sar adcs ... from the leader in high performance analog reference materials technical articles ? ms-2210: designing power supplies for high speed adc design resources ? ad7660 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7660 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7660?pecifications (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) rev. e ? parameter conditions min typ max unit resolution 16 bits analog input voltage range v in ?v ingnd 0v ref v operating input voltage v in ?.1 +3 v v ingnd ?.1 +0.5 v analog input cmrr f in = 25 khz 70 db input current 100 ksps throughput 325 na input impedance see analog input section throughput speed complete cycle 10 m s throughput rate 0 100 ksps dc accuracy integral linearity error ? +3 lsb 1 differential linearity error ? +1.75 lsb no missing codes 16 bits transition noise 2 0.75 lsb full-scale error 3 ref = 2.5 v 0.045 0.08 % of fsr unipolar zero error 3 1 5 lsb power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy signal-to-noise f in = 10 khz 87 90 db 4 f in = 45 khz 90 db spurious-free dynamic range f in = 10 khz 96 db f in = 45 khz 100 db total harmonic distortion f in = 10 khz ?6 db f in = 45 khz ?00 db signal-to-(noise+distortion) f in = 10 khz 87 db f in = 45 khz 90 db ?0 db input 30 db ? db input bandwidth 820 khz sampling dynamics aperture delay 2n s aperture jitter 5 ps rms transient response full-scale step 8 m s reference external reference voltage range 2.3 2.5 avdd ?1.85 v external reference current drain 100 ksps throughput 22 m a power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v operating current 100 ksps throughput avdd 3.2 ma dvdd 5 1m a ovdd 5 10 m a power dissipation 5 100 ksps throughput 21 25 mw 100 sps throughput 21 m w in power-down mode 5, 6 7 m w digital inputs logic levels v il ?.3 +0.8 v v ih +2.0 ovdd + 0.3 v i il ? +1 m a i ih ? +1 m a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = ?00 m a ovdd ?0.6 v
rev. e ? ad7660 parameter conditions min typ max unit temperature range specified performance t min to t max ?0 +85 c notes 1 lsb means least significant bit. with the 0 v to 2.5 v input range, one lsb is 38.15 m v. 2 typical rms noise at worst-case transitions and temperatures. 3 see definition of specifications section. these specifications do not include the error contribution from the external reference. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless otherwise specified. 5 tested in parallel reading mode. 6 with all digital inputs forced to dvdd or dgnd respectively. specifications subject to change without notice. (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) timing specifications parameter symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5n s time between conversions t 2 10 m s cnvst low to busy high delay t 3 15 ns busy high all modes except in t 4 2 m s master serial read after convert mode aperture delay t 5 2n s end of conversion to busy low delay t 6 10 ns conversion time t 7 2 m s acquisition time t 8 8 m s reset pulsewidth t 9 10 ns refer to figures 13, 14, and 15 (parallel interface modes) cnvst low to data valid delay t 10 2 m s data valid to busy low delay t 11 45 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 51 5 n s refer to figure 16 and 17 (master serial interface modes) 1 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 500 ns sync asserted to sclk first edge delay t 18 4n s internal sclk period t 19 40 75 ns internal sclk high (invsclk low) 2 t 20 30 ns internal sclk low (invsclk low) 2 t 21 9.5 ns sdout valid setup time t 22 4.5 ns sdout valid hold time t 23 3n s sclk last edge to sync delay t 24 3 cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert t 28 3.2 m s cnvst low to sync asserted delay t 29 1.5 m s sync deasserted to busy low delay t 30 50 ns refer to figures 18 and 20 (slave serial interface modes) 1 external sclk setup time t 31 5n s external sclk active edge to sdout delay t 32 31 6 n s sdin setup time t 33 5n s sdin hold time t 34 5n s external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns notes 1 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 2 if the polarity of sclk is inverted, the timing references of sclk are also inverted. specifications subject to change without notice.
rev. e ad7660 ? absolute maximum ratings 1 analog inputs in 2 , ref, ingnd, refgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avdd + 0.3 v to agnd ?0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . ?.3 v to +7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs except the databus d(7:4) . . . ?.3 v to dvdd + 0.3 v databus inputs d(7:4) . . . . . . ?.3 v to ovdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: q ja = 91 c/w, q jc = 30 c/w. 4 specification is for device in free air: 48-lead lfcsp: q ja = 26 c/w. i oh 500a 1.6ma i ol to output pin 1.4v c l 60pf * *in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing pin configuration t delay t delay 0.8v 0.8v 0.8v 2v 2v 2v figure 2. voltage reference levels for timings caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7660 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model 1 temperature range package description package option ?0 c to +85 c st-48 ?0 c to +85 c st-48 ?0 c to +85 c ad7660ast z ad7660ast z rl ad7660acp z rl notes 1 z = rohs compliant part. cp-48-4 48-lead lqfp 48-lead lqfp 48-lead lfcsp agnd avdd nc dgnd ob/2c nc nc ser/par d0 d1 d2 d3 agnd cnvst pd reset cs rd dgnd busy d15 d14 d13 d12 d4/ext/int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc in nc nc nc ingnd refgnd ref 24 23 22 21 20 19 18 17 1 6 15 14 13 44 45 46 47 48 43 42 41 40 39 38 37 ad7660 top view (not to scale) 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 notes 1. nc = no connect. do not connect to this pin. 2. the epad is connected to ground; how ever, this connection is not required to meet specified performance.
rev. e ad7660 ? pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p input analog power pins. nominally 5 v. 3, 6, 7, nc no connect 40?2, 44?8 4 dgnd di must be tied to digital ground 5ob/ 2c di straight binary/binary twos complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a twos complement output from its internal shift register. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9?2 d[0:3] do bit 0 to bit 3 of the parallel port data output bus. these pins are always outputs regardless of the state of ser/ par . 13 d4 di/o when ser/ par is low, this output is used as the bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. with ext/ int tied low, the internal clock is selected on the sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d5 di/o w hen ser/ par is low, this output is used as the bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. 15 d6 di/o w hen ser/ par is low, this output is used as the bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave modes. 16 d7 di/o when ser/ par is low, this output is used as the bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data is output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground 21 d8 do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on-chip register. the ad7660 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on the sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on the sclk falling edge and valid on the next rising edge.
rev. e ad7660 ? pin function descriptions (continued) pin no. mnemonic type description 22 d9 di/o when ser/ par is low, this output is used as bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 d10 do when ser/ par is low, this output is used as bit 10 of the parallel port data output bus. or sync when ser /par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 d11 do when ser/ par is low, this output is used as the bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started and not complete w hen the following conversion is complete, the current data is lost and rderror is pulsed high. 25?8 d[12:15] do bit 12 to bit 15 of the parallel port data output bus. these pins are always outputs regard- less of the state of ser/ par . 29 busy do busy output. transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data-ready clock signal. 30 dgnd p must be tied to digital ground 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, reset the ad7660. current conversion, if any, is aborted. 34 pd di power-down input. when set to a logic high, power consumption is reduced and conver- sions are inhibited after the current one is completed. 35 cnvst di start conversion. if cnvst is high when the acquisition phase (t 8 ) is complete, the next falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. this mode is the most appropriate if low sampling jitter is desired. if cnvst is low when the acquisition phase (t 8 ) is complete, the internal sample-and-hold is put into the hold state and a conversion is immediately started. 36 agnd p must be tied to analog ground 37 ref ai reference input voltage 38 refgnd ai reference input analog ground 39 ingnd ai analog input ground 43 in ai primary analog input with a range of 0 v to v ref notes ai = analog input di = digital input di/o = bidirectional digital do = digital output p = power epad exposed pad. the epad is connected to ground; however, this connection is not required to meet specified performance.
rev. e ad7660 ? definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from ?egative full scale?through ?ositive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is mea- sured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error t he last transition (from 011 . . . 10 to 011 . . . 11 in twos c omplement coding) should occur for an analog voltage 1 1/2 lsb b elow the nominal full scale (2.49994278 v for the 0 v?.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level 1/2 lsb above analog ground (19.073 m v for the 0 v?.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/[n+d] by the following formula: enob = s/ n + d db [] () ? /. 176 602 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic com ponents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response the time required for the ad7660 to achieve its rated accuracy after a full-scale step function is applied to its input. overvoltage recovery the time required for the adc to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value.
rev. e ad7660 ? ?ypical performance characteristics code ? 0 inl ?lsb 16384 ? ? 0 1 2 3 32768 49152 65536 tpc 1. integral nonlinearity vs. code code ?.00 0 dnl ?lsb 16384 0.00 32768 49152 65536 ?.75 0.50 1.00 1.75 1.50 1.25 0.75 0.25 ?.50 ?.25 tpc 4. differential nonlinearity vs. code frequency ?khz 010203 04050 amplitude ?db of full scale ?80 ?20 ?0 0 ?0 ?40 ?0 ?0 ?00 ?60 4096 point fft f s = 100khz f in = 45khz snr = 90.14db sinad = 89.94db thd = ?01.37db sfdr = 110db tpc 7. fft plot positive inl ?lsb 0 0 number of units 0.6 5 10 15 20 25 30 1.2 1.8 2.4 3.0 tpc 2. typical positive inl distribution (350 units) negative inl ?lsb 0 0 number of units ?.6 5 10 15 20 25 30 ?.2 ?.8 ?.4 ?.0 35 tpc 5. typical negative inl distribution (350 units) ?30 1 thd, harmonics ?db 10 100 1000 ?0 ?0 ?0 ?0 ?00 ?20 ?10 sfdr thd 60 sfdr ?db 90 100 120 110 80 70 second harmonic third harmonic frequency ?khz tpc 8. thd, harmonics, and sfdr vs. frequency code ?hex 0 counts 8008 8000 7000 6000 5000 4000 3000 2000 1000 0 8009 800a 800b 800c 800d 800e 800f 8010 8011 013 9 0 0 879 1213 7051 7219 tpc 3. histogram of 16,384 conversions of a dc input at the code transition code ?hex 0 counts 10000 8000 6000 4000 0 8009 800a 800b 800c 800d 800e 800f 8010 8011 0 188 00 161 2000 9026 3520 3489 tpc 6. histogram of 16,384 conversions of a dc input at the code center input level ?db ?40 ?0 thd, harmonics ?db ?0 ?0 ?0 ?0 ?00 ?20 ?10 thd second harmonic third harmonic ?0 0?0?0?0?0?0?0?0 ?30 tpc 9. thd, harmonics vs. input level
rev. e ad7660 ? frequency ?hz 1 snr and s/(n+d) ?db 10 100 1k snr s/(n+d) 13.0 enob ?bits 14.5 15.0 16.0 15.5 14.0 13.5 70 85 90 100 95 80 75 enob tpc 10. snr, s/(n+d), and enob vs. frequency sampling rate ?sps 10m 0.1 operating currents ?na 1m 100k 10k 1k 100 10 1 110 100 1k 10k 100k 1m av d d dvdd ovdd tpc 13. operating currents vs. sample rate c l ?pf 0 t 12 delay ?ns 50 100 200 0 20 30 50 40 10 150 ov dd @ 2.7v, 85 c ov dd @ 2.7v, 25 c ovdd @ 5v, 85 c ovdd @ 5v, 25 c tpc 12. typical delay vs. load capacitance c l ?2 ?0 ? ? ? ? 0 2 4 6 8 10 12 ?5 ?5 ?5 5 25 45 65 85 105 125 temperature (c) zero error, full scale error (lsb) full scale error zero error tpc 15. zero error, full scale vs. temperature input level ?db ?0 snr (referred to full scale) ?db ?0 ?0 0 86 90 92 88 ?0 ?0 tpc 11. snr vs. input level (referred to full scale) temperature ? c ?0 ?0 power-down operating currents ?na 10 60 110 50 60 100 80 20 0 10 ?5 35 85 30 40 70 90 dvdd av d d ovdd tpc 14. power-down operating currents vs. temperature
rev. e ad7660 ?0 circuit information the ad7660 is a fast, low power, single-supply, precise 16-bit analog-to-digital converter (adc). the ad7660 is capable of converting 100,000 samples per second (100 ksps) and allows power saving between conversions. when operating at 100 sps, for example, it consumes typically only 21 m w. this feature makes the ad7660 ideal for battery-powered applications. the ad7660 provides the user with an on-chip track-and- hold, successive-approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7660 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is ho used in a 48-lead lqfp package or a 48-lead lfcsp package that com- bines space savings and allows flexible configurations as either serial or parallel interface. the ad7660 is pin-to-pin compat ible with the ad7664. converter operation the ad7660 is a successive-approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows t he simplified schematic of the adc. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparator? negative input is connected to a ?ummy?capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparator? positive input is connected to agnd via sw a . all independent switches are connected to the analog input in. thus, the capacitor array is used as a sampling capaci- tor and acquires the analog signal on in input. similarly, the dummy capacitor acquires the analog signal on the ingnd input. when the acquisition phase is complete and the cnvst input goes or is low, a conversion phase is initiated. when the con- version phase begins, sw a and sw b are opened first. the capacitor array and the dummy capacitor are then discon nected from the inputs and connected to the refgnd input. there- fore, the differential voltage between in and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switch ing each element of the ca pacitor array between r efgnd or ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 . . . v ref /65536). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the comple- tion of this process, the control logic generates the adc output code and brings busy output low. sw a comp sw b in ref refgnd lsb lsb msb 32768c ingnd 16384c 4c 2c c 65536c control logic switches control busy output code cnvst c figure 3. adc simplified schematic
rev. e ad7660 ?1 100nf 10f 100nf 10f avdd 10f 100nf agnd dgnd dvdd ovdd ognd cs rd ser/ par cnvst busy sdout sclk reset pd in ingnd note 2 u1 refgnd c ref note 1 2.5v ref note 1 ref 100 d note 3 clock ad7660 analog input (0v to 2.5v) c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/ 2c notes 1. with the ad780 or the adr291 voltage reference, c ref is 47f, see voltage reference input section. 2. the op184 is recommended. 3. optional low jitter cnvst. figure 5. typical connection diagram transfer functions using the ob/ 2c digital input, the ad7660 offers two output codings: straight binary and twos complement. the lsb size is v ref /65536, which is about 38.15 m v. the ideal transfer charac- teristic for the ad7660 is shown in figure 4 and table ii. 000...000 000...001 000...010 111...101 111...110 111...111 adc code ?straight binary analog input v ref ?.5 lsb v ref ? lsb 1 lsb 0v 0.5 lsb 1 lsb = v ref /65536 figure 4. adc ideal transfer function table ii. output codes and ideal input voltages digital output code (hex) analog straight twos description input binary complement fsr ?1 lsb 2.499962 v ffff 1 7fff 1 fsr ?2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale ?1 lsb 1.249962 v 7fff ffff ?sr + 1 lsb 38 m v 0001 8001 ?sr 0 v 0000 2 8000 2 notes 1 this is also the code for overrange analog input (v in ?v ingnd above v ref ?v refgnd ). 2 this is also the code for underrange analog input (v in below v ingnd ). typical connection diagram figure 5 shows a typical connection diagram for the ad7660.
rev. e ad7660 ?2 analog input figure 6 shows an equivalent circuit of the input structure of the ad7660. c2 r1 d1 d2 c1 in or ingnd agnd avdd figure 6. equivalent analog input circuit the two diodes d1 and d2 provide esd protection for the analog inputs in and ingnd. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward- biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffer? (u1) supplies are different from avdd. in such cases, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differen tial signal between in and ingnd. unlike other converters, the ingnd input is sampled at the same time as the in input. by using this differential input, small signals common to both inputs are rejected as shown in figure 7, which represents the typical cmrr over frequency. for instance, by using ingnd to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground is eliminated. frequency ?hz cmrr ?db 45 75 10k 10m 1k 1m 80 65 100k 55 85 70 60 50 40 figure 7. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog input in can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. capacitor c1 is primarily the pin capacitance. the resistor r1 is typically 3242 w and is a lumped component made up of some serial resistors and the on resistance of the switches. the capacitor c2 is typically 60 pf and is mainly the adc sampling capaci tor. during the conversion phase, where the switches are opened, the input impedance is limited to c1. it has to be noted that the input impedance of the ad7660, unlike other sar adcs, is not a pure capacitance and thus, inherently reduces the kickback transient at the beginning of the acquisition phase. the r1, c2 makes a one- pole low-pass filter with a typical cutoff frequency of 820 khz that reduces undesirable aliasing effect and limits the noise. when the source impedance of the driving circuit is low, the ad7660 can be driven directly. large source impedances will significantly affect the ac performances, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades in function of the source impedance and the maximum input frequency as shown in figure 8. input frequency ?khz ?00 1 100 10 thd ?db ?5 ?0 ?5 ?0 ?5 ?0 r s = 500 r s = 100 r s = 50 r s = 20 figure 8. thd vs. analog input frequency and source resistance driver amplifier choice although the ad7660 is easy to drive, the driver amplifier needs to meet at least the following requirements: the driver amplifier and the ad7660 analog input circuit must be able, together, to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). for instance, operation at the maximum throughput of 100 ksps re quires a minimum gain bandwidth product of 5 mhz. the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi tion noise performance of the ad7660. the noise coming from the driver is filtered by the ad7660 analog input circuit one-pole low-pass filter made by r1 and c2. for instance, a driver with an equivalent input noise of 4 nv/ hz like the op184 and configured as a buffer, thus with a noise gain of +1, degrades the snr by only 0.1 db. the driver needs to have a thd performance suitable to that of the ad7660. tpc 8 gives the thd versus fre quency that the driver should preferably exceed. the snr degrada tion due to the amplifier is: snr fne loss db n = + ? ? ? ? ? ? 20 28 784 2 3 2 log () p where: f ? db is the ? db input bandwidth in mhz of the ad7660 (0.82 mhz) or the cutoff frequency of the input filter if any are used. n is the noise factor of the amplifier (1 if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/ hz .
rev. e ad7660 ?3 the ad8519, op162, or the op184 meet these requirements and are usually appropriate for almost all applications. as an alternative, in very high speed and noise-sensitive applications, the ad8021 with an external compensation capacitor of 10 pf or the ad829 with an external compensation capacitor of 82 pf c an be used. this capacitor should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. voltage reference input the ad7660 uses an external 2.5 v voltage reference. the voltage reference input ref of the ad7660 has a dynamic input impedance; it should therefore be driven by a low im pedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a 1 m f ceramic capacitor and a low esr tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. 47 m f is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: the low noise, low temperature drift adr421 and ad780 voltage references the low power adr291 voltage reference the low cost ad1582 voltage reference for applications using multiple ad7660s, it is more effective to buffer the reference voltage with a low noise, very stable op amp like the ad8031. care should also be taken with the reference temperature coeffi- cient of the voltage reference that directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. v ref , as mentioned in the specification table, could be in creased to avdd ?1.85 v. the benefit here is the increased snr obtained as a result of this increase. since the input range is defined in terms of v ref , this would essentially increase the range to make it a 3 v input range with an avdd above 4.85 v. the theoretical improvement as a result of this increase in refer ence is 1.58 db (20 log [3/2.5]). due to the theo retical quantization noise, however, the observed improve ment is ap proximately 1 db. the ad780 can be selected with a 3 v reference voltage. power supply the ad7660 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 5. the ad7660 is independent of power supply sequencing and thus free from supply voltage induced latch-up. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 9. input frequency ?hz psrr ?db ?0 1k 10k 100k 1m ?5 ?0 ?5 ?0 ?5 ?0 figure 9. psrr vs. frequency power dissipation vs. throughput the ad7660 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced, as shown in figure 10. this feature makes the ad7660 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the d igital inputs need to be driven close to the power rails (i.e., dvdd and dgnd for all inputs except ext/ int , invsync, i nvsclk, rdc/sdin, and ovdd or ognd for the last four inputs. throughput ?sps 10 100000 power dissipation ?w 100000 1000 10000 100 1 10 100 1000 10000 figure 10. power dissipation vs. sample rate
rev. e ad7660 ?4 conversion control figure 11 shows the detailed timing diagrams of the conversion process. the ad7660 is controlled by the signal cnvst , which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conver- sion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acq uire convert acquire convert figure 11. basic conversion timing for a true sampling application, the recommended operation of the cnvst signal is the following: cn vst must be held high from the previous falling edge of busy, and during a minimum delay corresponding to the acquisition time t 8 ; then, when cnvst is brought low, a conversion is initiated and the busy signal goes high until the completion of the conversion. although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. for applications where the snr is critical, the cnvst signal should have a very low jitter. this may be achieved by using a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency low jitter clock, as shown in figure 5. t 9 t 8 reset databus busy cnvst figure 12. reset timing for other applications, conversions can be automatically initi ated. if cnvst is held low when busy is low, the ad7660 controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the ad7660 keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7660 could some- times run slightly faster than the guaranteed limit of 100 ksps. digital interface the ad7660 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7660 digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the ad7660 to the host system interface digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals cs and rd control the interface. cs and rd have a similar effect because they are together internally. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7660 in multicircuit applications and is held low in a single ad7660 design. rd is generally used to enable the con- version result on the data bus. t 1 t 3 t 4 t 11 cnvst busy d ata bus cs = rd = 0 t 10 previous conversion data new data figure 13. master parallel data timing for reading (continuous read) parallel interface the ad7660 is configured to use the parallel interface when the ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in figures 14 and 15. when the data is read during the conversion, however, it is recommended that it is read-only during the first half of the conversion phase. this avoids any potential feedthrough be tween voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion busy data bus cs rd t 12 t 13 figure 14. slave parallel data timing for reading (read after convert)
rev. e ad7660 ?5 previous conversion t 1 t 3 t 12 t 13 t 4 cs = 0 cnvst, rd busy data bus figure 15. slave parallel data timing for reading (read during convert) serial interface the ad7660 is configured to use the serial interface when the ser/ par is held high. the ad7660 outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on the sclk pin. master serial interface internal clock the ad7660 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7660 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. the output data is valid on both the rising and falling edge of the data clock. depending on rdc/ sdin input, the data can be read after each conversion or during the following conversion. figures 16 and 17 show the detailed timing diagrams of these two modes. t 3 busy cs, rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 141516 d15 d14 d2 d1 d0 x ext/int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 figure 16. master serial data timing for reading (read after convert) ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy cs, rd cnvst sync sclk sdout figure 17. master serial data timing for reading (read previous conversion during convert)
rev. e ad7660 ?6 usually, because the ad7660 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. this makes the master read after conversion the most recommended serial mode when it can be used. in this mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. in read-during-conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. slave serial interface external clock the ad7660 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. when cs and rd are both low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or norm ally low when inactive. figures 18 and 20 show the detailed timing diagrams of these methods. usually, because the ad7660 has a longer acquisition phase than the conversion phase, the data are read immediately after conversion. while the ad7660 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is par- ticularly important during the second half of the conversion phase because the ad7660 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, it is a discon- tinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion this mode is the most recommended of the serial slave modes. figure 18 shows the detailed timing diagrams of this method. a fter a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs and rd are low. the data is shifted out, msb first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is the ability to read the data at any speed up to 40 mhz, which accommodates both slow digital host inter- face and the fastest serial reading. finally, in this mode only, the ad7660 provides a ?aisy-chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing compo nent count and wiring connections when it is desired as it is, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 19. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the opposite edge of sclk of the one used to shift out the data on sdout. therefore, the msb of the ?pstream converter just follows the lsb of the ?ownstream?converter on the next sclk cycle. up to 20 ad7660s running at 100 ksps can be daisy-chained using this method. sclk sdout rdc/sdin busy busy data out ad7660 #1 (downstream) bu sy out cnvst cs sclk ad7660 #2 (upstream) rdc/sdin sdout sclk in cs in cnvst in cnvst cs figure 19. two ad7660s in a daisy-chain configuration sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 cs busy sdin ext/int = 1 invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x14 x 123 14151 617 18 rd = 0 t 34 figure 18. slave serial data timing for reading (read after convert)
rev. e ad7660 ?7 external clock data read during conversion figure 20 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 16 clock pulses, and is valid on both the rising and falling edges of the clock. the 16 bits have to be read before the current conversion is complete; this, otherwise, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy- chain fea ture in this mode, and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of at least 18 mhz is recommended to ensure t hat all the bits are read during the first half of the conversion phase. for this reason, this mode is more difficult to use. microprocessor interfacing the ad7660 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal pro- cessing applications interfacing to a digital signal processor. the ad7660 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7660 to prevent digital noise from cou pling into the adc. the following section discusses t he use of an ad7660 with an adsp -219x spi equipped d sp. sdout cs sclk d1 d0 x d15 d14 d13 123 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16 cnvst busy ext/int = 1 invsclk = 0 rd = 0 figure 20. slave serial data timing for reading (read previous conversion during convert) spi interface (adsp-219x) figure 21 shows an interface diagram between the ad7660 and an spi-equipped adsp-219x. to accommodate the slower speed of the dsp, the ad7660 acts as a slave device and data must be read after conversion. this mode also allows the daisy- chain feature. the convert command can be initiated in response to an internal timer interrupt. the reading process cab be initi- ated in response to the end-of-conversion signal ( busy going low) using an interrupt line of the dsp. the serial interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (timod) = 00?by writing to the spi control register (spicltx). to meet all timing requirements, the spi clock should be limited to 17 mbps, which allows it to read an adc result in less than 1 m s. when a higher sampling rate is desired, use of one of the paral- lel interface modes is recommended. spixsel (pfx) adsp-219x* cnvst ad7660* cs busy misox sckx pfx or tfsx sdout sclk rd invsclk ext/int ser/par dvdd *additional pins omitted for clarity pfx figure 21. interfacing the ad7660 to an spi interface
rev. e ad7660 ?8 application hints bipolar and wider input ranges in some applications, it is desired to use a bipolar or wider analog input range like, for instance, 10 v, 5 v, or 0 v to 5 v. although the ad7660 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. figure 22 shows a connection diagram that allows this. compo- nent values required and resulting full-scale ranges are shown in table iii. u1 2.5v ref analog input r2 r3 r4 100nf r1 c f u2 c ref in ingnd ref refgnd 100nf ad7660 figure 22. using the ad7660 in 16-bit bipolar and/or wider input ranges table iii. component values and input ranges input range r1 (k w ) r2 ( k w ) r3 ( k w ) r4 ( k w ) 10 v 1 8 10 8 5 v 1 4 10 6.67 0 v to ? v 1 2 none 0 for bipolar range applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer u2, as shown in figure 22. also, c f can be used as a one-pole antialiasing filter. layout the ad7660 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. t he printed circuit board that houses the ad7660 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of g round planes that can be easily separated. digital and ana- log ground planes should be joined in only one place, preferably underneath the ad7660, or, at least, as close as possible to the ad7660. if the ad7660 is in a system where multiple devices r equire analog to digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7660. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane s hould be allowed to run under the ad7660 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7660 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supply? impedance presented to the ad7660 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply pins avdd, dvdd, and ovdd close to, and ideally right up against, these pins and their corresponding ground pins. additionally, low esr 10 m f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. t he dvdd supply of the ad7660 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recom- mended if no separate supply is available, to connect the dvdd digital supply to the analog supply avdd through an rc filter as shown in figure 6 and to connect the system supply to the inter face digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7660 has five different ground pins: ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depend- ing on the configuration. ognd is connected to the digital sys tem ground.
rev. e ad7660 ?9 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 40. 48-lead plastic quad flat package [lqfp] (st-48) dimensions shown in millimeters 112408-b for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wkkd. 1 0.50 bsc bottom view top view pin 1 indicator 7.00 bsc sq 48 13 24 25 36 37 12 exposed pad p i n 1 i n d i c a t o r 5.20 5.10 sq 5.00 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 figure 41. 48-lead lead frame chip scale package [lfcsp] 7 x 7 mm body and 0.75 mm package height (cp-48-4) dimensions shown in millimeters
rev. e ?0 ad7660 d01928-0-2/16(e) revision history location page 10/03?ata sheet changed from rev. c to rev. d. update format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added pulsar selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 added overvoltage recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 added tpc 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to circuit information section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 renamed table i to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 5 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 8 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to driver amplifier choise section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 replaced figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 changes to digital interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 replaced figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 deleted figure 22 and renumbered successive figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 replaced microprocessor interfacing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes in bipolar and wider input ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes to table iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 added cp-48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 update outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1/02?ata sheet changed from rev. b to rev. c. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 new voltage reference input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to digital interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 new st-48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9/01?ata sheet changed from rev. a to rev. b. edit to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edit to timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to typical performance characteristics graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 10 edit to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edit to figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edit to figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 edit to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 edit to bipolar and wider input ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 / 1 6 data sheet changed from rev. d to rev. e . update outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 deleted e valuating the ad7660 p erformance section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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